Dr. Swarnalatha Radhakrishnan

Admin

Dr. Swarnalatha Radhakrishnan

Senior Lecturer

BIO

Senior Lecturer since 2007 with teaching and research experience in Computer Architecture and Embedded Systems. Completed her Bachelors Degree in Electronics Engineering from IT-BHU, Varanasi (now Indian Institute of Technology, Varanasi) and PhD in Computer Science and Engineering from the University of New South Wales.

Educational Qualifications:
  • B.Tech (Electronics)
  • Ph.D. (CSE)
Available for Supervision:
  • Yes
Research projects supervised by Dr. Swarnalatha Radhakrishnan:
Applying deep learning on histological images of lymph tissues
Applying deep learning on histological images of lymph tissues

Please note that here only contain the 'Projects' which were submitted to the projects.ce.pdn.ac.lk as Final Year Research Projects. The actual list of projects supervised by Dr. Swarnalatha Radhakrishnan may be longer than this.

Research Interests:
  • Computer Architecture
  • Embedded Systems
  • Computer Interfacing
  • Memory Hierarchy Design
Publications:
  • Exploring multilevel cache hierarchies in application specific mpsocs
    Isuru Nawinne, Haris Javaid, Roshan Ragel , Swarnalatha Radhakrishnan , Sri Parameswaran
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015
    doi: 10.1109/TCAD.2015.2445736
    #Algorithm design and analysis#Hardware#Program processors#Space exploration#Integrated circuit modeling#Mathematical model#Optimization
  • Exploring multilevel cache hierarchies in application specific mpsocs
    Isuru Nawinne, Haris Javaid, Roshan Ragel , Swarnalatha Radhakrishnan , Sri Parameswaran
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015
    doi: 10.1109/TCAD.2015.2445736
    #Algorithm design and analysis#Hardware#Program processors#Space exploration#Integrated circuit modeling#Mathematical model#Optimization
  • A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors
    Roshan G. Ragel , Swarnalatha Radhakrishnan , Jude Angelo Ambrose, Sri Parameswaran
    2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013
    doi: 10.1109/VLSID.2013.154
    [ PDF (Preprint) ]
    #Hardware#Thumb#Embedded systems#Benchmark testing#Standards#Instruction sets
  • CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors
    Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan , Roshan Ragel , Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
    2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
    doi: 10.7873/DATE.2013.152
    #Redundancy#Time factors#Runtime#Integrated circuits#Programming
  • DRMA: dynamically reconfigurable MPSoC architecture
    Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan Ragel , Swarnalatha Radhakrishnan , Kewal K. Saluja
    GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, 2013
    doi: 10.1145/2483028.2483101
    #Computer systems organization#Architectures#Serial architectures#Pipeline computing#Hardware

Please note that here only contain the 'Publications' affiliated with the Department of Computer Engineering, which were submitted to the site. To see the full publication profile, visit the ResearchGate or Google Scholar profile.